44 void set_chip_model(chip_model model);
45 void set_voice_mask(reg4 mask);
46 void enable_filter(
bool enable);
47 void adjust_filter_bias(
double dac_bias);
48 void enable_external_filter(
bool enable);
49 bool set_sampling_parameters(
double clock_freq, sampling_method method,
50 double sample_freq,
double pass_freq = -1,
51 double filter_scale = 0.97);
52 void adjust_sampling_frequency(
double sample_freq);
53 void enable_raw_debug_output(
bool enable);
56 void clock(cycle_count delta_t);
57 int clock(cycle_count& delta_t,
short* buf,
int n,
int interleave = 1);
61 reg8 read(reg8 offset);
62 void write(reg8 offset, reg8 value);
70 char sid_register[0x20];
73 cycle_count bus_value_ttl;
74 cycle_count write_pipeline;
79 reg24 shift_register[3];
80 cycle_count shift_register_reset[3];
81 cycle_count shift_pipeline[3];
82 reg16 pulse_output[3];
83 cycle_count floating_output_ttl[3];
85 reg16 rate_counter[3];
86 reg16 rate_counter_period[3];
87 reg16 exponential_counter[3];
88 reg16 exponential_counter_period[3];
89 reg8 envelope_counter[3];
90 EnvelopeGenerator::State envelope_state[3];
92 cycle_count envelope_pipeline[3];
96 void write_state(
const State& state);
99 void input(
short sample);
104 void debugoutput(
void);
107 static double I0(
double x);
108 int clock_fast(cycle_count& delta_t,
short* buf,
int n,
int interleave);
109 int clock_interpolate(cycle_count& delta_t,
short* buf,
int n,
int interleave);
110 int clock_resample(cycle_count& delta_t,
short* buf,
int n,
int interleave);
111 int clock_resample_fastmem(cycle_count& delta_t,
short* buf,
int n,
int interleave);
114 chip_model sid_model;
122 cycle_count bus_value_ttl;
125 cycle_count databus_ttl;
128 cycle_count write_pipeline;
131 double clock_frequency;
146 FIR_RES_FASTMEM = 51473,
150 RINGMASK = RINGSIZE - 1,
158 sampling_method sampling;
159 cycle_count cycles_per_sample;
160 cycle_count sample_offset;
162 short sample_prev, sample_now;
166 double fir_f_cycles_per_sample;
167 double fir_filter_scale;
175 bool raw_debug_output;